System Design

DSP processing systems.

FPGA Coding

VHDL or Verilog, Xilinx or Intel.

Matlab Models

Professionally coded reference model.


Simple testbenches to System Verilog formal verification


Porting existing designs to VHDL.


State of the Art in signal processing.

Why FulcrumDSP ?

Today's FPGA solutions have become so complicated that engineers who don't do FPGA design every day are finding the tools too complicated and overwhelming to operate properly. This is true regardless of whether the engineer is using Xilinx Vivado, or Intel(Altera) Quartus. In some cases, the promise of design ease employing higher level design entry tools such as Simulink have just not panned out as well as the sales brochure would indicate. Regardless of whether you are reworking an existing design, or starting a new design from scratch, FulcrumDSP is ready.

The most common starting points we see are:

1) Blank sheet, new system design. In this case, we very much prefer to work with the customer system engineers to create a Matlab system model (m-code) to use as a baseline for the new design. This model will serve as a reference for the new design, and will be used to validate the new design.

2) Existing VHDL or Verilog design to be reworked or enhanced. Depending on the state of the existing design, this can be seamless, or can be very costly. In some of the more extreme cases, we may insist on reworking the existing design prior to doing add-on work.

3) Existing high level model(usually Simulink). There are actually two variants to this.

A) In one variant, the Simulink model is simply a system model no different than an m-code model. In this case the hand-off is usually seamless.

B) The second variant is where the Simulink model employs the Xilinx "System Generator" blockset library, or the Intel(Altera) "DSP Builder" blockset library for direct FPGA targeting. This variant is much more complex, and has been abandoned by most customer who have explored this option. We can help convert these type of models back to VHDL or Verilog so that they are again maintainable.


FPGA System testing can range in scope from minimal to extensive depending on the use case. One of the biggest mistakes customers make in testing DSP systems is excepting "sunny day" test results. Even broken DSP systems can usually output a simple signal, or operate under ideal conditions, but the real testing of a DSP system includes measuring the effects of truncation to fixed point; plotting impulse responses; measuring the response to Gaussian, impulse, and narrow-band noise; and formal verification against a full floating-point mathematical system model. These tests could be performed in simulation, or in system, or both, depending on the nature of the system. In some mission critical systems, the formal verification may include statistical analysis, Monte-Carlo rounds, and dynamically predictive systems such as those possible with SystemVerilog. Regardless of the level of testing required, FulcrumDSP has the expertise to make the program a success.